OpenWrt – Blame information for rev 1
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| Rev | Author | Line No. | Line |
|---|---|---|---|
| 1 | office | 1 | /* |
| 2 | * ADM5120 interrupt controller definitions |
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| 3 | * |
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| 4 | * This header file defines the hardware registers of the ADM5120 SoC |
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| 5 | * built-in interrupt controller. |
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| 6 | * |
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| 7 | * Copyright (C) 2007-2008 Gabor Juhos <juhosg@openwrt.org> |
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| 8 | * |
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| 9 | * This program is free software; you can redistribute it and/or modify it |
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| 10 | * under the terms of the GNU General Public License version 2 as published |
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| 11 | * by the Free Software Foundation. |
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| 12 | * |
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| 13 | */ |
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| 14 | |||
| 15 | #ifndef _MACH_ADM5120_INTC_H |
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| 16 | #define _MACH_ADM5120_INTC_H |
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| 17 | |||
| 18 | /* |
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| 19 | * INTC register offsets |
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| 20 | */ |
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| 21 | #define INTC_REG_IRQ_STATUS 0x00 /* Interrupt status after masking */ |
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| 22 | #define INTC_REG_IRQ_RAW_STATUS 0x04 /* Interrupt status before masking */ |
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| 23 | #define INTC_REG_IRQ_ENABLE 0x08 /* Used to enable the interrupt sources */ |
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| 24 | #define INTC_REG_IRQ_ENABLE_CLEAR 0x0C /* Used to disable the interrupt sources */ |
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| 25 | #define INTC_REG_IRQ_DISABLE INTC_REG_IRQ_ENABLE_CLEAR |
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| 26 | #define INTC_REG_INT_MODE 0x14 /* The interrupt mode of the sources */ |
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| 27 | #define INTC_REG_FIQ_STATUS 0x18 /* FIQ status */ |
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| 28 | #define INTC_REG_IRQ_TEST_SOURCE 0x1C |
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| 29 | #define INTC_REG_IRQ_SOURCE_SELECT 0x20 |
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| 30 | #define INTC_REG_INT_LEVEL 0x24 |
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| 31 | |||
| 32 | /* |
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| 33 | * INTC IRQ numbers |
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| 34 | */ |
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| 35 | #define INTC_IRQ_TIMER 0 /* built in timer */ |
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| 36 | #define INTC_IRQ_UART0 1 /* built-in UART0 */ |
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| 37 | #define INTC_IRQ_UART1 2 /* built-in UART1 */ |
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| 38 | #define INTC_IRQ_USBC 3 /* USB Host Controller */ |
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| 39 | #define INTC_IRQ_GPIO2 4 /* GPIO line 2 */ |
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| 40 | #define INTC_IRQ_GPIO4 5 /* GPIO line 4 */ |
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| 41 | #define INTC_IRQ_PCI0 6 /* PCI slot 2 */ |
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| 42 | #define INTC_IRQ_PCI1 7 /* PCI slot 3 */ |
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| 43 | #define INTC_IRQ_PCI2 8 /* PCI slot 4 */ |
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| 44 | #define INTC_IRQ_SWITCH 9 /* built-in ethernet switch */ |
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| 45 | #define INTC_IRQ_LAST INTC_IRQ_SWITCH |
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| 46 | #define INTC_IRQ_COUNT 10 |
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| 47 | |||
| 48 | /* |
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| 49 | * INTC register bits |
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| 50 | */ |
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| 51 | #define INTC_INT_TIMER (1 << INTC_IRQ_TIMER) |
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| 52 | #define INTC_INT_UART0 (1 << INTC_IRQ_UART0) |
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| 53 | #define INTC_INT_UART1 (1 << INTC_IRQ_UART1) |
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| 54 | #define INTC_INT_USBC (1 << INTC_IRQ_USBC) |
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| 55 | #define INTC_INT_INTX0 (1 << INTC_IRQ_INTX0) |
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| 56 | #define INTC_INT_INTX1 (1 << INTC_IRQ_INTX1) |
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| 57 | #define INTC_INT_PCI0 (1 << INTC_IRQ_PCI0) |
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| 58 | #define INTC_INT_PCI1 (1 << INTC_IRQ_PCI1) |
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| 59 | #define INTC_INT_PCI2 (1 << INTC_IRQ_PCI2) |
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| 60 | #define INTC_INT_SWITCH (1 << INTC_IRQ_SWITCH) |
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| 61 | #define INTC_INT_ALL ((1 << INTC_IRQ_COUNT) - 1) |
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| 62 | |||
| 63 | #endif /* _MACH_ADM5120_INTC_H */ |