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1 office 1 /******************************************************************************
2  
3 Copyright (c) 2009
4 Infineon Technologies AG
5 Am Campeon 1-12; 81726 Munich, Germany
6  
7 For licensing information, see the file 'LICENSE' in the root folder of
8 this software module.
9  
10 ******************************************************************************/
11  
12 #ifndef IFXMIPS_MEI_H
13 #define IFXMIPS_MEI_H
14  
15 //#define CONFIG_AMAZON_SE 1
16 //#define CONFIG_DANUBE 1
17 //#define CONFIG_AR9 1
18  
19 #if !defined(CONFIG_DANUBE) && !defined(CONFIG_AMAZON_SE) && !defined(CONFIG_AR9) && !defined(CONFIG_VR9)
20 #error Platform undefined!!!
21 #endif
22  
23 #ifdef IFX_MEI_BSP
24 /** This is the character datatype. */
25 typedef char DSL_char_t;
26 /** This is the unsigned 8-bit datatype. */
27 typedef unsigned char DSL_uint8_t;
28 /** This is the signed 8-bit datatype. */
29 typedef signed char DSL_int8_t;
30 /** This is the unsigned 16-bit datatype. */
31 typedef unsigned short DSL_uint16_t;
32 /** This is the signed 16-bit datatype. */
33 typedef signed short DSL_int16_t;
34 /** This is the unsigned 32-bit datatype. */
35 typedef unsigned long DSL_uint32_t;
36 /** This is the signed 32-bit datatype. */
37 typedef signed long DSL_int32_t;
38 /** This is the float datatype. */
39 typedef float DSL_float_t;
40 /** This is the void datatype. */
41 typedef void DSL_void_t;
42 /** integer type, width is depending on processor arch */
43 typedef int DSL_int_t;
44 /** unsigned integer type, width is depending on processor arch */
45 typedef unsigned int DSL_uint_t;
46 typedef struct file DSL_DRV_file_t;
47 typedef struct inode DSL_DRV_inode_t;
48  
49 /**
50 * Defines all possible CMV groups
51 * */
52 typedef enum {
53 DSL_CMV_GROUP_CNTL = 1,
54 DSL_CMV_GROUP_STAT = 2,
55 DSL_CMV_GROUP_INFO = 3,
56 DSL_CMV_GROUP_TEST = 4,
57 DSL_CMV_GROUP_OPTN = 5,
58 DSL_CMV_GROUP_RATE = 6,
59 DSL_CMV_GROUP_PLAM = 7,
60 DSL_CMV_GROUP_CNFG = 8
61 } DSL_CmvGroup_t;
62 /**
63 * Defines all opcode types
64 * */
65 typedef enum {
66 H2D_CMV_READ = 0x00,
67 H2D_CMV_WRITE = 0x04,
68 H2D_CMV_INDICATE_REPLY = 0x10,
69 H2D_ERROR_OPCODE_UNKNOWN =0x20,
70 H2D_ERROR_CMV_UNKNOWN =0x30,
71  
72 D2H_CMV_READ_REPLY =0x01,
73 D2H_CMV_WRITE_REPLY = 0x05,
74 D2H_CMV_INDICATE = 0x11,
75 D2H_ERROR_OPCODE_UNKNOWN = 0x21,
76 D2H_ERROR_CMV_UNKNOWN = 0x31,
77 D2H_ERROR_CMV_READ_NOT_AVAILABLE = 0x41,
78 D2H_ERROR_CMV_WRITE_ONLY = 0x51,
79 D2H_ERROR_CMV_READ_ONLY = 0x61,
80  
81 H2D_DEBUG_READ_DM = 0x02,
82 H2D_DEBUG_READ_PM = 0x06,
83 H2D_DEBUG_WRITE_DM = 0x0a,
84 H2D_DEBUG_WRITE_PM = 0x0e,
85  
86 D2H_DEBUG_READ_DM_REPLY = 0x03,
87 D2H_DEBUG_READ_FM_REPLY = 0x07,
88 D2H_DEBUG_WRITE_DM_REPLY = 0x0b,
89 D2H_DEBUG_WRITE_FM_REPLY = 0x0f,
90 D2H_ERROR_ADDR_UNKNOWN = 0x33,
91  
92 D2H_AUTONOMOUS_MODEM_READY_MSG = 0xf1
93 } DSL_CmvOpcode_t;
94  
95 /* mutex macros */
96 #define MEI_MUTEX_INIT(id,flag) \
97 sema_init(&id,flag)
98 #define MEI_MUTEX_LOCK(id) \
99 down_interruptible(&id)
100 #define MEI_MUTEX_UNLOCK(id) \
101 up(&id)
102 #define MEI_WAIT(ms) \
103 {\
104 set_current_state(TASK_INTERRUPTIBLE);\
105 schedule_timeout(ms);\
106 }
107 #define MEI_INIT_WAKELIST(name,queue) \
108 init_waitqueue_head(&queue)
109  
110 static inline long
111 ugly_hack_sleep_on_timeout(wait_queue_head_t *q, long timeout)
112 {
113 unsigned long flags;
114 #if (LINUX_VERSION_CODE >= KERNEL_VERSION(4,13,0))
115 wait_queue_entry_t wait;
116 #else
117 wait_queue_t wait;
118 #endif
119  
120 init_waitqueue_entry(&wait, current);
121  
122 __set_current_state(TASK_INTERRUPTIBLE);
123 spin_lock_irqsave(&q->lock, flags);
124 __add_wait_queue(q, &wait);
125 spin_unlock(&q->lock);
126  
127 timeout = schedule_timeout(timeout);
128  
129 spin_lock_irq(&q->lock);
130 __remove_wait_queue(q, &wait);
131 spin_unlock_irqrestore(&q->lock, flags);
132  
133 return timeout;
134 }
135  
136 /* wait for an event, timeout is measured in ms */
137 #define MEI_WAIT_EVENT_TIMEOUT(ev,timeout)\
138 ugly_hack_sleep_on_timeout(&ev, timeout * HZ / 1000)
139 #define MEI_WAKEUP_EVENT(ev)\
140 wake_up_interruptible(&ev)
141 #endif /* IFX_MEI_BSP */
142  
143 /*** Register address offsets, relative to MEI_SPACE_ADDRESS ***/
144 #define ME_DX_DATA (0x0000)
145 #define ME_VERSION (0x0004)
146 #define ME_ARC_GP_STAT (0x0008)
147 #define ME_DX_STAT (0x000C)
148 #define ME_DX_AD (0x0010)
149 #define ME_DX_MWS (0x0014)
150 #define ME_ME2ARC_INT (0x0018)
151 #define ME_ARC2ME_STAT (0x001C)
152 #define ME_ARC2ME_MASK (0x0020)
153 #define ME_DBG_WR_AD (0x0024)
154 #define ME_DBG_RD_AD (0x0028)
155 #define ME_DBG_DATA (0x002C)
156 #define ME_DBG_DECODE (0x0030)
157 #define ME_CONFIG (0x0034)
158 #define ME_RST_CTRL (0x0038)
159 #define ME_DBG_MASTER (0x003C)
160 #define ME_CLK_CTRL (0x0040)
161 #define ME_BIST_CTRL (0x0044)
162 #define ME_BIST_STAT (0x0048)
163 #define ME_XDATA_BASE_SH (0x004c)
164 #define ME_XDATA_BASE (0x0050)
165 #define ME_XMEM_BAR_BASE (0x0054)
166 #define ME_XMEM_BAR0 (0x0054)
167 #define ME_XMEM_BAR1 (0x0058)
168 #define ME_XMEM_BAR2 (0x005C)
169 #define ME_XMEM_BAR3 (0x0060)
170 #define ME_XMEM_BAR4 (0x0064)
171 #define ME_XMEM_BAR5 (0x0068)
172 #define ME_XMEM_BAR6 (0x006C)
173 #define ME_XMEM_BAR7 (0x0070)
174 #define ME_XMEM_BAR8 (0x0074)
175 #define ME_XMEM_BAR9 (0x0078)
176 #define ME_XMEM_BAR10 (0x007C)
177 #define ME_XMEM_BAR11 (0x0080)
178 #define ME_XMEM_BAR12 (0x0084)
179 #define ME_XMEM_BAR13 (0x0088)
180 #define ME_XMEM_BAR14 (0x008C)
181 #define ME_XMEM_BAR15 (0x0090)
182 #define ME_XMEM_BAR16 (0x0094)
183  
184 #define WHILE_DELAY 20000
185 /*
186 ** Define where in ME Processor's memory map the Stratify chip lives
187 */
188  
189 #define MAXSWAPSIZE (8 * 1024) //8k *(32bits)
190  
191 // Mailboxes
192 #define MSG_LENGTH 16 // x16 bits
193 #define YES_REPLY 1
194 #define NO_REPLY 0
195  
196 #define CMV_TIMEOUT 1000 //jiffies
197  
198 // Block size per BAR
199 #define SDRAM_SEGMENT_SIZE (64*1024)
200 // Number of Bar registers
201 #define MAX_BAR_REGISTERS (17)
202  
203 #define XDATA_REGISTER (15)
204  
205 // ARC register addresss
206 #define ARC_STATUS 0x0
207 #define ARC_LP_START 0x2
208 #define ARC_LP_END 0x3
209 #define ARC_DEBUG 0x5
210 #define ARC_INT_MASK 0x10A
211  
212 #define IRAM0_BASE (0x00000)
213 #define IRAM1_BASE (0x04000)
214 #if defined(CONFIG_DANUBE)
215 #define BRAM_BASE (0x0A000)
216 #elif defined(CONFIG_AMAZON_SE) || defined(CONFIG_AR9) || defined(CONFIG_VR9)
217 #define BRAM_BASE (0x08000)
218 #endif
219 #define XRAM_BASE (0x18000)
220 #define YRAM_BASE (0x1A000)
221 #define EXT_MEM_BASE (0x80000)
222 #define ARC_GPIO_CTRL (0xC030)
223 #define ARC_GPIO_DATA (0xC034)
224  
225 #define IRAM0_SIZE (16*1024)
226 #define IRAM1_SIZE (16*1024)
227 #define BRAM_SIZE (12*1024)
228 #define XRAM_SIZE (8*1024)
229 #define YRAM_SIZE (8*1024)
230 #define EXT_MEM_SIZE (1536*1024)
231  
232 #define ADSL_BASE (0x20000)
233 #define CRI_BASE (ADSL_BASE + 0x11F00)
234 #define CRI_CCR0 (CRI_BASE + 0x00)
235 #define CRI_RST (CRI_BASE + 0x04*4)
236 #define ADSL_DILV_BASE (ADSL_BASE+0x20000)
237  
238 //
239 #define IRAM0_ADDR_BIT_MASK 0xFFF
240 #define IRAM1_ADDR_BIT_MASK 0xFFF
241 #define BRAM_ADDR_BIT_MASK 0xFFF
242 #define RX_DILV_ADDR_BIT_MASK 0x1FFF
243  
244 /*** Bit definitions ***/
245 #define ARC_AUX_HALT (1 << 25)
246 #define ARC_DEBUG_HALT (1 << 1)
247 #define FALSE 0
248 #define TRUE 1
249 #define BIT0 (1<<0)
250 #define BIT1 (1<<1)
251 #define BIT2 (1<<2)
252 #define BIT3 (1<<3)
253 #define BIT4 (1<<4)
254 #define BIT5 (1<<5)
255 #define BIT6 (1<<6)
256 #define BIT7 (1<<7)
257 #define BIT8 (1<<8)
258 #define BIT9 (1<<9)
259 #define BIT10 (1<<10)
260 #define BIT11 (1<<11)
261 #define BIT12 (1<<12)
262 #define BIT13 (1<<13)
263 #define BIT14 (1<<14)
264 #define BIT15 (1<<15)
265 #define BIT16 (1<<16)
266 #define BIT17 (1<<17)
267 #define BIT18 (1<<18)
268 #define BIT19 (1<<19)
269 #define BIT20 (1<<20)
270 #define BIT21 (1<<21)
271 #define BIT22 (1<<22)
272 #define BIT23 (1<<23)
273 #define BIT24 (1<<24)
274 #define BIT25 (1<<25)
275 #define BIT26 (1<<26)
276 #define BIT27 (1<<27)
277 #define BIT28 (1<<28)
278 #define BIT29 (1<<29)
279 #define BIT30 (1<<30)
280 #define BIT31 (1<<31)
281  
282 // CRI_CCR0 Register definitions
283 #define CLK_2M_MODE_ENABLE BIT6
284 #define ACL_CLK_MODE_ENABLE BIT4
285 #define FDF_CLK_MODE_ENABLE BIT2
286 #define STM_CLK_MODE_ENABLE BIT0
287  
288 // CRI_RST Register definitions
289 #define FDF_SRST BIT3
290 #define MTE_SRST BIT2
291 #define FCI_SRST BIT1
292 #define AAI_SRST BIT0
293  
294 // MEI_TO_ARC_INTERRUPT Register definitions
295 #define MEI_TO_ARC_INT1 BIT3
296 #define MEI_TO_ARC_INT0 BIT2
297 #define MEI_TO_ARC_CS_DONE BIT1 //need to check
298 #define MEI_TO_ARC_MSGAV BIT0
299  
300 // ARC_TO_MEI_INTERRUPT Register definitions
301 #define ARC_TO_MEI_INT1 BIT8
302 #define ARC_TO_MEI_INT0 BIT7
303 #define ARC_TO_MEI_CS_REQ BIT6
304 #define ARC_TO_MEI_DBG_DONE BIT5
305 #define ARC_TO_MEI_MSGACK BIT4
306 #define ARC_TO_MEI_NO_ACCESS BIT3
307 #define ARC_TO_MEI_CHECK_AAITX BIT2
308 #define ARC_TO_MEI_CHECK_AAIRX BIT1
309 #define ARC_TO_MEI_MSGAV BIT0
310  
311 // ARC_TO_MEI_INTERRUPT_MASK Register definitions
312 #define GP_INT1_EN BIT8
313 #define GP_INT0_EN BIT7
314 #define CS_REQ_EN BIT6
315 #define DBG_DONE_EN BIT5
316 #define MSGACK_EN BIT4
317 #define NO_ACC_EN BIT3
318 #define AAITX_EN BIT2
319 #define AAIRX_EN BIT1
320 #define MSGAV_EN BIT0
321  
322 #define MEI_SOFT_RESET BIT0
323  
324 #define HOST_MSTR BIT0
325  
326 #define JTAG_MASTER_MODE 0x0
327 #define MEI_MASTER_MODE HOST_MSTR
328  
329 // MEI_DEBUG_DECODE Register definitions
330 #define MEI_DEBUG_DEC_MASK (0x3)
331 #define MEI_DEBUG_DEC_AUX_MASK (0x0)
332 #define ME_DBG_DECODE_DMP1_MASK (0x1)
333 #define MEI_DEBUG_DEC_DMP2_MASK (0x2)
334 #define MEI_DEBUG_DEC_CORE_MASK (0x3)
335  
336 #define AUX_STATUS (0x0)
337 #define AUX_ARC_GPIO_CTRL (0x10C)
338 #define AUX_ARC_GPIO_DATA (0x10D)
339 // ARC_TO_MEI_MAILBOX[11] is a special location used to indicate
340 // page swap requests.
341 #if defined(CONFIG_DANUBE)
342 #define OMBOX_BASE 0xDF80
343 #define ARC_TO_MEI_MAILBOX 0xDFA0
344 #define IMBOX_BASE 0xDFC0
345 #define MEI_TO_ARC_MAILBOX 0xDFD0
346 #elif defined(CONFIG_AMAZON_SE) || defined(CONFIG_AR9) || defined(CONFIG_VR9)
347 #define OMBOX_BASE 0xAF80
348 #define ARC_TO_MEI_MAILBOX 0xAFA0
349 #define IMBOX_BASE 0xAFC0
350 #define MEI_TO_ARC_MAILBOX 0xAFD0
351 #endif
352  
353 #define MEI_TO_ARC_MAILBOXR (MEI_TO_ARC_MAILBOX + 0x2C)
354 #define ARC_MEI_MAILBOXR (ARC_TO_MEI_MAILBOX + 0x2C)
355 #define OMBOX1 (OMBOX_BASE+0x4)
356  
357 // Codeswap request messages are indicated by setting BIT31
358 #define OMB_CODESWAP_MESSAGE_MSG_TYPE_MASK (0x80000000)
359  
360 // Clear Eoc messages received are indicated by setting BIT17
361 #define OMB_CLEAREOC_INTERRUPT_CODE (0x00020000)
362 #define OMB_REBOOT_INTERRUPT_CODE (1 << 18)
363  
364 /*
365 ** Swap page header
366 */
367 // Page must be loaded at boot time if size field has BIT31 set
368 #define BOOT_FLAG (BIT31)
369 #define BOOT_FLAG_MASK ~BOOT_FLAG
370  
371 #define FREE_RELOAD 1
372 #define FREE_SHOWTIME 2
373 #define FREE_ALL 3
374  
375 // marcos
376 #define IFX_MEI_WRITE_REGISTER_L(data,addr) *((volatile u32*)(addr)) = (u32)(data)
377 #define IFX_MEI_READ_REGISTER_L(addr) (*((volatile u32*)(addr)))
378 #define SET_BIT(reg, mask) reg |= (mask)
379 #define CLEAR_BIT(reg, mask) reg &= (~mask)
380 #define CLEAR_BITS(reg, mask) CLEAR_BIT(reg, mask)
381 //#define SET_BITS(reg, mask) SET_BIT(reg, mask)
382 #define SET_BITFIELD(reg, mask, off, val) {reg &= (~mask); reg |= (val << off);}
383  
384 #define ALIGN_SIZE ( 1L<<10 ) //1K size align
385 #define MEM_ALIGN(addr) (((addr) + ALIGN_SIZE - 1) & ~ (ALIGN_SIZE -1) )
386  
387 // swap marco
388 #define MEI_HALF_WORD_SWAP(data) {data = ((data & 0xffff)<<16) + ((data & 0xffff0000)>>16);}
389 #define MEI_BYTE_SWAP(data) {data = ((data & 0xff)<<24) + ((data & 0xff00)<<8)+ ((data & 0xff0000)>>8)+ ((data & 0xff000000)>>24);}
390  
391  
392 #ifdef CONFIG_PROC_FS
393 typedef struct reg_entry
394 {
395 int *flag;
396 char name[30]; /* big enough to hold names */
397 char description[100]; /* big enough to hold description */
398 unsigned short low_ino;
399 } reg_entry_t;
400 #endif
401 // Swap page header describes size in 32-bit words, load location, and image offset
402 // for program and/or data segments
403 typedef struct _arc_swp_page_hdr {
404 u32 p_offset; //Offset bytes of progseg from beginning of image
405 u32 p_dest; //Destination addr of progseg on processor
406 u32 p_size; //Size in 32-bitwords of program segment
407 u32 d_offset; //Offset bytes of dataseg from beginning of image
408 u32 d_dest; //Destination addr of dataseg on processor
409 u32 d_size; //Size in 32-bitwords of data segment
410 } ARC_SWP_PAGE_HDR;
411  
412 /*
413 ** Swap image header
414 */
415 #define GET_PROG 0 // Flag used for program mem segment
416 #define GET_DATA 1 // Flag used for data mem segment
417  
418 // Image header contains size of image, checksum for image, and count of
419 // page headers. Following that are 'count' page headers followed by
420 // the code and/or data segments to be loaded
421 typedef struct _arc_img_hdr {
422 u32 size; // Size of binary image in bytes
423 u32 checksum; // Checksum for image
424 u32 count; // Count of swp pages in image
425 ARC_SWP_PAGE_HDR page[1]; // Should be "count" pages - '1' to make compiler happy
426 } ARC_IMG_HDR;
427  
428 typedef struct smmu_mem_info {
429 int type;
430 int boot;
431 unsigned long nCopy;
432 unsigned long size;
433 unsigned char *address;
434 unsigned char *org_address;
435 } smmu_mem_info_t;
436  
437 #ifdef __KERNEL__
438 typedef struct ifx_mei_device_private {
439 int modem_ready;
440 int arcmsgav;
441 int cmv_reply;
442 int cmv_waiting;
443 // Mei to ARC CMV count, reply count, ARC Indicator count
444 int modem_ready_cnt;
445 int cmv_count;
446 int reply_count;
447 unsigned long image_size;
448 int nBar;
449 u16 Recent_indicator[MSG_LENGTH];
450  
451 u16 CMV_RxMsg[MSG_LENGTH] __attribute__ ((aligned (4)));
452  
453 smmu_mem_info_t adsl_mem_info[MAX_BAR_REGISTERS];
454 ARC_IMG_HDR *img_hdr;
455 // to wait for arc cmv reply, sleep on wait_queue_arcmsgav;
456 wait_queue_head_t wait_queue_arcmsgav;
457 wait_queue_head_t wait_queue_modemready;
458 struct semaphore mei_cmv_sema;
459 } ifx_mei_device_private_t;
460 #endif
461 typedef struct winhost_message {
462 union {
463 u16 RxMessage[MSG_LENGTH] __attribute__ ((aligned (4)));
464 u16 TxMessage[MSG_LENGTH] __attribute__ ((aligned (4)));
465 } msg;
466 } DSL_DEV_WinHost_Message_t;
467 /********************************************************************************************************
468 * DSL CPE API Driver Stack Interface Definitions
469 * *****************************************************************************************************/
470 /** IOCTL codes for bsp driver */
471 #define DSL_IOC_MEI_BSP_MAGIC 's'
472  
473 #define DSL_FIO_BSP_DSL_START _IO (DSL_IOC_MEI_BSP_MAGIC, 0)
474 #define DSL_FIO_BSP_RUN _IO (DSL_IOC_MEI_BSP_MAGIC, 1)
475 #define DSL_FIO_BSP_FREE_RESOURCE _IO (DSL_IOC_MEI_BSP_MAGIC, 2)
476 #define DSL_FIO_BSP_RESET _IO (DSL_IOC_MEI_BSP_MAGIC, 3)
477 #define DSL_FIO_BSP_REBOOT _IO (DSL_IOC_MEI_BSP_MAGIC, 4)
478 #define DSL_FIO_BSP_HALT _IO (DSL_IOC_MEI_BSP_MAGIC, 5)
479 #define DSL_FIO_BSP_BOOTDOWNLOAD _IO (DSL_IOC_MEI_BSP_MAGIC, 6)
480 #define DSL_FIO_BSP_JTAG_ENABLE _IO (DSL_IOC_MEI_BSP_MAGIC, 7)
481 #define DSL_FIO_FREE_RESOURCE _IO (DSL_IOC_MEI_BSP_MAGIC, 8)
482 #define DSL_FIO_ARC_MUX_TEST _IO (DSL_IOC_MEI_BSP_MAGIC, 9)
483 #define DSL_FIO_BSP_REMOTE _IOW (DSL_IOC_MEI_BSP_MAGIC, 10, u32)
484 #define DSL_FIO_BSP_GET_BASE_ADDRESS _IOR (DSL_IOC_MEI_BSP_MAGIC, 11, u32)
485 #define DSL_FIO_BSP_IS_MODEM_READY _IOR (DSL_IOC_MEI_BSP_MAGIC, 12, u32)
486 #define DSL_FIO_BSP_GET_VERSION _IOR (DSL_IOC_MEI_BSP_MAGIC, 13, DSL_DEV_Version_t)
487 #define DSL_FIO_BSP_CMV_WINHOST _IOWR(DSL_IOC_MEI_BSP_MAGIC, 14, DSL_DEV_WinHost_Message_t)
488 #define DSL_FIO_BSP_CMV_READ _IOWR(DSL_IOC_MEI_BSP_MAGIC, 15, DSL_DEV_MeiReg_t)
489 #define DSL_FIO_BSP_CMV_WRITE _IOW (DSL_IOC_MEI_BSP_MAGIC, 16, DSL_DEV_MeiReg_t)
490 #define DSL_FIO_BSP_DEBUG_READ _IOWR(DSL_IOC_MEI_BSP_MAGIC, 17, DSL_DEV_MeiDebug_t)
491 #define DSL_FIO_BSP_DEBUG_WRITE _IOWR(DSL_IOC_MEI_BSP_MAGIC, 18, DSL_DEV_MeiDebug_t)
492 #define DSL_FIO_BSP_GET_CHIP_INFO _IOR (DSL_IOC_MEI_BSP_MAGIC, 19, DSL_DEV_HwVersion_t)
493  
494 #define DSL_DEV_MEIDEBUG_BUFFER_SIZES 512
495  
496 typedef struct DSL_DEV_MeiDebug
497 {
498 DSL_uint32_t iAddress;
499 DSL_uint32_t iCount;
500 DSL_uint32_t buffer[DSL_DEV_MEIDEBUG_BUFFER_SIZES];
501 } DSL_DEV_MeiDebug_t; /* meidebug */
502  
503 /**
504 * Structure is used for debug access only.
505 * Refer to configure option INCLUDE_ADSL_WINHOST_DEBUG */
506 typedef struct struct_meireg
507 {
508 /*
509 * Specifies that address for debug access */
510 unsigned long iAddress;
511 /*
512 * Specifies the pointer to the data that has to be written or returns a
513 * pointer to the data that has been read out*/
514 unsigned long iData;
515 } DSL_DEV_MeiReg_t; /* meireg */
516  
517 typedef struct DSL_DEV_Device
518 {
519 DSL_int_t nInUse; /* modem state, update by bsp driver, */
520 DSL_void_t *pPriv;
521 DSL_uint32_t base_address; /* mei base address */
522 DSL_int_t nIrq[2]; /* irq number */
523 #define IFX_DFEIR 0
524 #define IFX_DYING_GASP 1
525 DSL_DEV_MeiDebug_t lop_debugwr; /* dying gasp */
526 #if (LINUX_VERSION_CODE > KERNEL_VERSION(2,6,0))
527 struct module *owner;
528 #endif
529 } DSL_DEV_Device_t; /* ifx_adsl_device_t */
530  
531 #define DSL_DEV_PRIVATE(dev) ((ifx_mei_device_private_t*)(dev->pPriv))
532  
533 typedef struct DSL_DEV_Version /* ifx_adsl_bsp_version */
534 {
535 unsigned long major;
536 unsigned long minor;
537 unsigned long revision;
538 } DSL_DEV_Version_t; /* ifx_adsl_bsp_version_t */
539  
540 typedef struct DSL_DEV_ChipInfo
541 {
542 unsigned long major;
543 unsigned long minor;
544 } DSL_DEV_HwVersion_t;
545  
546 typedef struct
547 {
548 DSL_uint8_t dummy;
549 } DSL_DEV_DeviceConfig_t;
550  
551 /** error code definitions */
552 typedef enum DSL_DEV_MeiError
553 {
554 DSL_DEV_MEI_ERR_SUCCESS = 0,
555 DSL_DEV_MEI_ERR_FAILURE = -1,
556 DSL_DEV_MEI_ERR_MAILBOX_FULL = -2,
557 DSL_DEV_MEI_ERR_MAILBOX_EMPTY = -3,
558 DSL_DEV_MEI_ERR_MAILBOX_TIMEOUT = -4
559 } DSL_DEV_MeiError_t; /* MEI_ERROR */
560  
561 typedef enum {
562 DSL_BSP_MEMORY_READ=0,
563 DSL_BSP_MEMORY_WRITE,
564 } DSL_BSP_MemoryAccessType_t; /* ifx_adsl_memory_access_type_t */
565  
566 typedef enum
567 {
568 DSL_LED_LINK_ID=0,
569 DSL_LED_DATA_ID
570 } DSL_DEV_LedId_t; /* ifx_adsl_led_id_t */
571  
572 typedef enum
573 {
574 DSL_LED_LINK_TYPE=0,
575 DSL_LED_DATA_TYPE
576 } DSL_DEV_LedType_t; /* ifx_adsl_led_type_t */
577  
578 typedef enum
579 {
580 DSL_LED_HD_CPU=0,
581 DSL_LED_HD_FW
582 } DSL_DEV_LedHandler_t; /* ifx_adsl_led_handler_t */
583  
584 typedef enum {
585 DSL_LED_ON=0,
586 DSL_LED_OFF,
587 DSL_LED_FLASH,
588 } DSL_DEV_LedMode_t; /* ifx_adsl_led_mode_t */
589  
590 typedef enum {
591 DSL_CPU_HALT=0,
592 DSL_CPU_RUN,
593 DSL_CPU_RESET,
594 } DSL_DEV_CpuMode_t; /* ifx_adsl_cpu_mode_t */
595  
596 #if 0
597 typedef enum {
598 DSL_BSP_EVENT_DYING_GASP = 0,
599 DSL_BSP_EVENT_CEOC_IRQ,
600 } DSL_BSP_Event_id_t; /* ifx_adsl_event_id_t */
601  
602 typedef union DSL_BSP_CB_Param
603 {
604 DSL_uint32_t nIrqMessage;
605 } DSL_BSP_CB_Param_t; /* ifx_adsl_cbparam_t */
606  
607 typedef struct DSL_BSP_CB_Event
608 {
609 DSL_BSP_Event_id_t nID;
610 DSL_DEV_Device_t *pDev;
611 DSL_BSP_CB_Param_t *pParam;
612 } DSL_BSP_CB_Event_t; /* ifx_adsl_cb_event_t */
613 #endif
614  
615 /* external functions (from the BSP Driver) */
616 extern DSL_DEV_Device_t* DSL_BSP_DriverHandleGet(int, int);
617 extern DSL_int_t DSL_BSP_DriverHandleDelete(DSL_DEV_Device_t *);
618 extern DSL_DEV_MeiError_t DSL_BSP_FWDownload(DSL_DEV_Device_t *, const DSL_char_t *, DSL_uint32_t, DSL_int32_t *, DSL_int32_t *);
619 extern int DSL_BSP_KernelIoctls(DSL_DEV_Device_t *, unsigned int, unsigned long);
620 extern DSL_DEV_MeiError_t DSL_BSP_SendCMV(DSL_DEV_Device_t *, DSL_uint16_t *, DSL_int_t, DSL_uint16_t *);
621 extern DSL_DEV_MeiError_t DSL_BSP_AdslLedInit(DSL_DEV_Device_t *, DSL_DEV_LedId_t, DSL_DEV_LedType_t, DSL_DEV_LedHandler_t);
622 extern DSL_DEV_MeiError_t DSL_BSP_Showtime(DSL_DEV_Device_t *, DSL_uint32_t, DSL_uint32_t);
623 extern int DSL_BSP_ATMLedCBRegister( int (*ifx_adsl_ledcallback)(void));
624 extern DSL_DEV_MeiError_t DSL_BSP_MemoryDebugAccess(DSL_DEV_Device_t *, DSL_BSP_MemoryAccessType_t, DSL_uint32_t, DSL_uint32_t *, DSL_uint32_t);
625 extern volatile DSL_DEV_Device_t *adsl_dev;
626  
627 /**
628 * Dummy structure by now to show mechanism of extended data that will be
629 * provided within event callback itself.
630 * */
631 typedef struct
632 {
633 /**
634 * Dummy value */
635 DSL_uint32_t nDummy1;
636 } DSL_BSP_CB_Event1DataDummy_t;
637  
638 /**
639 * Dummy structure by now to show mechanism of extended data that will be
640 * provided within event callback itself.
641 * */
642 typedef struct
643 {
644 /**
645 * Dummy value */
646 DSL_uint32_t nDummy2;
647 } DSL_BSP_CB_Event2DataDummy_t;
648  
649 /**
650 * encapsulate all data structures that are necessary for status event
651 * callbacks.
652 * */
653 typedef union
654 {
655 DSL_BSP_CB_Event1DataDummy_t dataEvent1;
656 DSL_BSP_CB_Event2DataDummy_t dataEvent2;
657 } DSL_BSP_CB_DATA_Union_t;
658  
659  
660 typedef enum
661 {
662 /**
663 * Informs the upper layer driver (DSL CPE API) about a reboot request from the
664 * firmware.
665 * \note This event does NOT include any additional data.
666 * More detailed information upon reboot reason has to be requested from
667 * upper layer software via CMV (INFO 109) if necessary. */
668 DSL_BSP_CB_FIRST = 0,
669 DSL_BSP_CB_DYING_GASP,
670 DSL_BSP_CB_CEOC_IRQ,
671 DSL_BSP_CB_FIRMWARE_REBOOT,
672 /**
673 * Delimiter only */
674 DSL_BSP_CB_LAST
675 } DSL_BSP_CB_Type_t;
676  
677 /**
678 * Specifies the common event type that has to be used for registering and
679 * signalling of interrupts/autonomous status events from MEI BSP Driver.
680 *
681 * \param pDev
682 * Context pointer from MEI BSP Driver.
683 *
684 * \param IFX_ADSL_BSP_CallbackType_t
685 * Specifies the event callback type (reason of callback). Regrading to the
686 * setting of this value the data which is included in the following union
687 * might have different meanings.
688 * Please refer to the description of the union to get information about the
689 * meaning of the included data.
690 *
691 * \param pData
692 * Data according to \ref DSL_BSP_CB_DATA_Union_t.
693 * If this pointer is NULL there is no additional data available.
694 *
695 * \return depending on event
696 */
697 typedef int (*DSL_BSP_EventCallback_t)
698 (
699 DSL_DEV_Device_t *pDev,
700 DSL_BSP_CB_Type_t nCallbackType,
701 DSL_BSP_CB_DATA_Union_t *pData
702 );
703  
704 typedef struct {
705 DSL_BSP_EventCallback_t function;
706 DSL_BSP_CB_Type_t event;
707 DSL_BSP_CB_DATA_Union_t *pData;
708 } DSL_BSP_EventCallBack_t;
709  
710 extern int DSL_BSP_EventCBRegister(DSL_BSP_EventCallBack_t *);
711 extern int DSL_BSP_EventCBUnregister(DSL_BSP_EventCallBack_t *);
712  
713 /** Modem states */
714 #define DSL_DEV_STAT_InitState 0x0000
715 #define DSL_DEV_STAT_ReadyState 0x0001
716 #define DSL_DEV_STAT_FailState 0x0002
717 #define DSL_DEV_STAT_IdleState 0x0003
718 #define DSL_DEV_STAT_QuietState 0x0004
719 #define DSL_DEV_STAT_GhsState 0x0005
720 #define DSL_DEV_STAT_FullInitState 0x0006
721 #define DSL_DEV_STAT_ShowTimeState 0x0007
722 #define DSL_DEV_STAT_FastRetrainState 0x0008
723 #define DSL_DEV_STAT_LoopDiagMode 0x0009
724 #define DSL_DEV_STAT_ShortInit 0x000A /* Bis short initialization */
725  
726 #define DSL_DEV_STAT_CODESWAP_COMPLETE 0x0002
727  
728 #endif //IFXMIPS_MEI_H