OpenWrt – Blame information for rev 2

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1 office 1 From a58eb20fb80f478038243e9e0f30f6984725e265 Mon Sep 17 00:00:00 2001
2 From: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
3 Date: Tue, 6 Jan 2015 15:47:18 +0100
4 Subject: sun6i: Sync PLL1 multipliers/dividers with Boot1
5  
6 This change syncs up the multipliers and dividers used to initialize
7 PLL1 (i.e. the fast clock driving the ARM cores) with the values used
8 in Allwinner's Boot1 on sun6i.
9  
10 More specifically, the following settings are now used:
11 * up to 768MHz: mul=2, div=2 (was: mul=1, div=1)
12 * up to 1152MHz: mul=3, div=2 (unchanged)
13 * above 1152MHz: mul=4, div=2 (was: mul=2, div=1)
14  
15 --- a/arch/arm/mach-sunxi/clock_sun6i.c
16 +++ b/arch/arm/mach-sunxi/clock_sun6i.c
17 @@ -112,11 +112,12 @@ void clock_set_pll1(unsigned int clk)
18 struct sunxi_ccm_reg * const ccm =
19 (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
20 const int p = 0;
21 - int k = 1;
22 - int m = 1;
23 + int k = 2;
24 + int m = 2;
25  
26 if (clk > 1152000000) {
27 - k = 2;
28 + k = 4;
29 + m = 2;
30 } else if (clk > 768000000) {
31 k = 3;
32 m = 2;