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1 office 1 From patchwork Tue Jan 20 11:28:45 2015
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5 Subject: [OpenWrt-Devel] uboot-lantiq cgu settings for ramboot image
6 From: Ben Mulvihill <ben.mulvihill@gmail.com>
7 X-Patchwork-Id: 431024
8 Message-Id: <1421753325.25187.58.camel@merveille.lan>
9 To: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
10 Cc: OpenWrt Development List <openwrt-devel@lists.openwrt.org>
11 Date: Tue, 20 Jan 2015 12:28:45 +0100
12  
13 On Tue, 2015-01-20 at 00:39 +0100, Ben Mulvihill wrote:
14 > On Mon, 2015-01-19 at 19:21 +0100, Ben Mulvihill wrote:
15 > > On Mon, 2015-01-19 at 16:47 +0100, Daniel Schwierzeck wrote:
16 > > > 2015-01-19 15:44 GMT+01:00 Ben Mulvihill <ben.mulvihill@gmail.com>:
17 > > > > On Mon, 2015-01-19 at 11:51 +0000, Conor O'Gorman wrote:
18 > > > >> On 19/01/15 10:46, Ben Mulvihill wrote:
19 > > > >> > Hello,
20 > > > >> >
21 > > > >> > I am trying to build uboot-lantiq for the BT Home Hub 3A (lantiq
22 > > > >> > ar9), and am wondering where to initialise the cgu, in the case
23 > > > >> > of a ramboot image for uart booting. Normally the cgu is initialised
24 > > > >> > in lowlevel_init, but that code is bypassed in ramboot images. The
25 > > > >> > result is that the board boots with the wrong cgu settings, which
26 > > > >> > sends the console haywire. So far I have tried two solutions:
27 > > > >>
28 > > > >> Another option is to try and not change anything. The console is already
29 > > > >> configured and running. The ram does need config.
30 > > > >>
31 > > > >> I was used to seeing the ramboot version running at half clock speed, at
32 > > > >> least on danube, previous to ar9.
33 > > > >>
34 > > > >> Conor
35 > > > >
36 > > > > Hi Conor,
37 > > > >
38 > > > > Thanks for the reply. But with the latest uboot-lantiq, not changing
39 > > > > anything means that I don't get a usable console. With an older
40 > > > > version I do at least get a uboot console, but no linux console when
41 > > > > I boot openwrt. Correcting the cgu settings solves both problems.
42 > > > >
43 > > >
44 > > > could you try this?
45 > > >
46 > > > diff --git a/arch/mips/cpu/mips32/arx100/cgu.c
47 > > > b/arch/mips/cpu/mips32/arx100/cgu.c
48 > > > index 6e71ee7..e0afbda 100644
49 > > > --- a/arch/mips/cpu/mips32/arx100/cgu.c
50 > > > +++ b/arch/mips/cpu/mips32/arx100/cgu.c
51 > > > @@ -95,15 +95,5 @@ unsigned long ltq_get_cpu_clock(void)
52 > > >
53 > > > unsigned long ltq_get_bus_clock(void)
54 > > > {
55 > > > - u32 fpi_sel;
56 > > > - unsigned long clk;
57 > > > -
58 > > > - fpi_sel = ltq_cgu_sys_readl(1, CGU_SYS_FPI_SEL);
59 > > > -
60 > > > - if (fpi_sel)
61 > > > - clk = ltq_get_io_region_clock() / 2;
62 > > > - else
63 > > > - clk = ltq_get_io_region_clock();
64 > > > -
65 > > > - return clk;
66 > > > + return ltq_get_io_region_clock();
67 > > > }
68 > > >
69 > > > the UART driver calculates the baudrate from the FPI bus clock, but
70 > > > FPI_SEL is not available on AR9. FPI bus clock is always the same as
71 > > > DDR clock, Obviously a copy&paste error from VR9 code ;)
72 > > >
73 > >
74 > > No, even with this patch, I still don't get a working console I'm
75 > > afraid. If I don't set anything explicitly, the board comes up with
76 > > CGU_SYS set to 0x05, ie CGU_SYS_SYSSEL_PLL0_333_MHZ |
77 > > CGU_SYS_CPUSEL_EQUAL_DDRCLK | CGU_SYS_DDRSEL_THIRD_SYSCLK.
78 > > Is this a valid combination without CGU_SYS_PPESEL_250_MHZ ?
79 > > I don't understand what CGU_SYS_PPESEL_250_MHZ does?
80 > > The "right setting", as set by the stock uboot, is 0x80.
81 >
82 > P.S. There also seems to be a discrepancy between the uboot and
83 > linux code. I take it from what you say above that fpi clock, ddr
84 > clock and io region clock are all the same. Now if the least
85 > significant bit of CGU_SYS is set, then according to the uboot
86 > code - function ltq_get_bus_clock() - their value is one
87 > third of the system clock. But according to the linux code
88 > - function ltq_ar9_fpi_hz() in arch/mips/lantiq/xway/clk.c -
89 > their value in this case is equal to the system clock.
90 >
91 > Or am I getting muddled? It's past my bedtime!
92 >
93 >
94  
95 Some of the bitshifting in arch/mips/cpu/mips32/arx100/cgu.c is 1
96 out. A patch along these lines should fix it:
97  
98 --- a/arch/mips/cpu/mips32/arx100/cgu.c
99 +++ b/arch/mips/cpu/mips32/arx100/cgu.c
100 @@ -10,12 +10,17 @@
101 #include <asm/lantiq/clk.h>
102 #include <asm/lantiq/io.h>
103  
104 -#define CGU_SYS_DDR_SEL (1 << 0)
105 -#define CGU_SYS_CPU_SEL (1 << 2)
106 +#define CGU_SYS_DDR_SHIFT 0
107 +#define CGU_SYS_CPU_SHIFT 2
108 #define CGU_SYS_SYS_SHIFT 3
109 +#define CGU_SYS_FPI_SHIFT 6
110 +#define CGU_SYS_PPE_SHIFT 7
111 +
112 +#define CGU_SYS_DDR_MASK (1 << CGU_SYS_DDR_SHIFT)
113 +#define CGU_SYS_CPU_MASK (1 << CGU_SYS_CPU_SHIFT)
114 #define CGU_SYS_SYS_MASK (0x3 << CGU_SYS_SYS_SHIFT)
115 -#define CGU_SYS_FPI_SEL (1 << 6)
116 -#define CGU_SYS_PPE_SEL (1 << 7)
117 +#define CGU_SYS_FPI_MASK (1 << CGU_SYS_FPI_SHIFT)
118 +#define CGU_SYS_PPE_MASK (1 << CGU_SYS_PPE_SHIFT)
119  
120 struct ltq_cgu_regs {
121 u32 rsvd0;
122 @@ -68,7 +73,7 @@ unsigned long ltq_get_io_region_clock(vo
123 u32 ddr_sel;
124 unsigned long clk;
125  
126 - ddr_sel = ltq_cgu_sys_readl(1, CGU_SYS_DDR_SEL);
127 + ddr_sel = ltq_cgu_sys_readl(CGU_SYS_DDR_MASK, CGU_SYS_DDR_SHIFT);
128  
129 if (ddr_sel)
130 clk = ltq_get_system_clock() / 3;
131 @@ -83,7 +88,7 @@ unsigned long ltq_get_cpu_clock(void)
132 u32 cpu_sel;
133 unsigned long clk;
134  
135 - cpu_sel = ltq_cgu_sys_readl(1, CGU_SYS_CPU_SEL);
136 + cpu_sel = ltq_cgu_sys_readl(CGU_SYS_CPU_MASK, CGU_SYS_CPU_SHIFT);
137  
138 if (cpu_sel)
139 clk = ltq_get_io_region_clock();
140 @@ -98,7 +103,7 @@ unsigned long ltq_get_bus_clock(void)
141 u32 fpi_sel;
142 unsigned long clk;
143  
144 - fpi_sel = ltq_cgu_sys_readl(1, CGU_SYS_FPI_SEL);
145 + fpi_sel = ltq_cgu_sys_readl(CGU_SYS_FPI_MASK, CGU_SYS_FPI_SHIFT);
146  
147 if (fpi_sel)
148 clk = ltq_get_io_region_clock() / 2;