OpenWrt – Blame information for rev 3
?pathlinks?
Rev | Author | Line No. | Line |
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1 | office | 1 | |
2 | arm: kirkwood: add ZyXEL NSA310 device |
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3 | |||
4 | This patch add ZyXEL NSA310 1-Bay Media Server |
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5 | |||
6 | The ZyXEL NSA310 device is a Kirkwood based NAS: |
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7 | |||
8 | - SoC: Marvell 88F6702 1200Mhz |
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9 | - SDRAM memory: 256MB DDR2 400Mhz |
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10 | - Gigabit ethernet: PHY Realtek |
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11 | - Flash memory: 128MB |
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12 | - 1 Power button |
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13 | - 1 Power LED (blue) |
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14 | - 5 Status LED (green/red) |
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15 | - 1 Copy/Sync button |
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16 | - 1 Reset button |
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17 | - 2 SATA II port (1 internal and 1 external eSata) |
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18 | - 2 USB 2.0 ports (1 front and 1 back) |
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19 | - Smart fan |
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20 | |||
21 | Signed-off-by: Alberto Bursi <alberto.bursi@outlook.it> |
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22 | |||
23 | NOTE: this patch is ready for upstream, LEDE-specific parts are in |
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24 | another patch |
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25 | |||
26 | --- a/arch/arm/mach-kirkwood/Kconfig |
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27 | +++ b/arch/arm/mach-kirkwood/Kconfig |
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28 | @@ -56,6 +56,9 @@ config TARGET_GOFLEXHOME |
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29 | config TARGET_NAS220 |
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30 | bool "BlackArmor NAS220" |
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3 | office | 31 | |
1 | office | 32 | +config TARGET_NSA310 |
33 | + bool "Zyxel NSA310 Board" |
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34 | + |
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35 | config TARGET_NSA310S |
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36 | bool "Zyxel NSA310S" |
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3 | office | 37 | |
38 | @@ -80,6 +83,7 @@ source "board/raidsonic/ib62x0/Kconfig" |
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1 | office | 39 | source "board/Seagate/dockstar/Kconfig" |
40 | source "board/Seagate/goflexhome/Kconfig" |
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41 | source "board/Seagate/nas220/Kconfig" |
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42 | +source "board/zyxel/nsa310/Kconfig" |
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43 | source "board/zyxel/nsa310s/Kconfig" |
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3 | office | 44 | |
45 | endif |
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1 | office | 46 | --- /dev/null |
47 | +++ b/board/zyxel/nsa310/Kconfig |
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48 | @@ -0,0 +1,12 @@ |
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49 | +if TARGET_NSA310 |
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50 | + |
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51 | +config SYS_BOARD |
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52 | + default "nsa310" |
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53 | + |
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54 | +config SYS_VENDOR |
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55 | + default "zyxel" |
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56 | + |
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57 | +config SYS_CONFIG_NAME |
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58 | + default "nsa310" |
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59 | + |
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60 | +endif |
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61 | --- /dev/null |
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62 | +++ b/board/zyxel/nsa310/MAINTAINERS |
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63 | @@ -0,0 +1,6 @@ |
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64 | +NSA310 BOARD |
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65 | +M: Alberto Bursi <alberto.bursi@outlook.it> |
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66 | +S: Maintained |
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67 | +F: board/zyxel/nsa310/ |
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68 | +F: include/configs/nsa310.h |
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69 | +F: configs/nsa310_defconfig |
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70 | --- /dev/null |
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71 | +++ b/board/zyxel/nsa310/Makefile |
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72 | @@ -0,0 +1,12 @@ |
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73 | +# |
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74 | +# (C) Copyright 2015 bodhi <mibodhi@gmail.com> |
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75 | +# |
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76 | +# Based on |
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77 | +# (C) Copyright 2009 |
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78 | +# Marvell Semiconductor <www.marvell.com> |
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79 | +# Written-by: Prafulla Wadaskar <prafulla@marvell.com> |
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80 | +# |
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81 | +# SPDX-License-Identifier: GPL-2.0+ |
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82 | +# |
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83 | + |
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84 | +obj-y := nsa310.o |
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85 | --- /dev/null |
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86 | +++ b/board/zyxel/nsa310/kwbimage.cfg |
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87 | @@ -0,0 +1,166 @@ |
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88 | +# |
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89 | +# Copyright (C) 2013 Rafal Kazmierowski |
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90 | +# |
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91 | +# Based on guruplug.c originally written by |
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92 | +# Siddarth Gore <gores@marvell.com> |
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93 | +# (C) Copyright 2009 |
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94 | +# Marvell Semiconductor <www.marvell.com> |
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95 | +# |
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96 | +# See file CREDITS for list of people who contributed to this |
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97 | +# project. |
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98 | +# |
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99 | +# This program is free software; you can redistribute it and/or |
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100 | +# modify it under the terms of the GNU General Public License as |
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101 | +# published by the Free Software Foundation; either version 2 of |
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102 | +# the License, or (at your option) any later version. |
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103 | +# |
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104 | +# This program is distributed in the hope that it will be useful, |
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105 | +# but WITHOUT ANY WARRANTY; without even the implied warranty of |
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106 | +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
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107 | +# GNU General Public License for more details. |
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108 | +# |
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109 | +# You should have received a copy of the GNU General Public License |
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110 | +# along with this program; if not, write to the Free Software |
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111 | +# Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, |
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112 | +# MA 02110-1301 USA |
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113 | +# |
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114 | +# Refer docs/README.kwimage for more details about how-to configure |
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115 | +# and create kirkwood boot image |
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116 | +# |
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117 | + |
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118 | +# Boot Media configurations |
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119 | +BOOT_FROM nand |
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120 | +#BOOT_FROM uart |
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121 | +NAND_ECC_MODE default |
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122 | +NAND_PAGE_SIZE 0x0800 |
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123 | + |
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124 | +# SOC registers configuration using bootrom header extension |
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125 | +# Maximum KWBIMAGE_MAX_CONFIG configurations allowed |
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126 | + |
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127 | +# Configure RGMII-0 interface pad voltage to 1.8V |
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128 | +DATA 0xFFD100e0 0x1b1b1b9b |
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129 | + |
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130 | +#Dram initalization for SINGLE x16 CL=5 @ 400MHz |
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131 | +DATA 0xFFD01400 0x43010c30 # DDR Configuration register |
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132 | +# bit13-0: 0xc30 (3120 DDR2 clks refresh rate) |
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133 | +# bit23-14: zero |
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134 | +# bit24: 1= enable exit self refresh mode on DDR access |
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135 | +# bit25: 1 required |
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136 | +# bit29-26: zero |
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137 | +# bit31-30: 01 |
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138 | + |
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139 | +DATA 0xFFD01404 0x37543000 # DDR Controller Control Low |
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140 | +# bit 4: 0=addr/cmd in smame cycle |
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141 | +# bit 5: 0=clk is driven during self refresh, we don't care for APX |
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142 | +# bit 6: 0=use recommended falling edge of clk for addr/cmd |
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143 | +# bit14: 0=input buffer always powered up |
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144 | +# bit18: 1=cpu lock transaction enabled |
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145 | +# bit23-20: 5=recommended value for CL=5 and STARTBURST_DEL disabled bit31=0 |
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146 | +# bit27-24: 7= CL+2, STARTBURST sample stages, for freqs 400MHz, unbuffered DIMM |
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147 | +# bit30-28: 3 required |
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148 | +# bit31: 0=no additional STARTBURST delay |
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149 | + |
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150 | +DATA 0xFFD01408 0x22125451 # DDR Timing (Low) (active cycles value +1) |
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151 | +# bit3-0: TRAS lsbs |
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152 | +# bit7-4: TRCD |
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153 | +# bit11- 8: TRP |
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154 | +# bit15-12: TWR |
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155 | +# bit19-16: TWTR |
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156 | +# bit20: TRAS msb |
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157 | +# bit23-21: 0x0 |
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158 | +# bit27-24: TRRD |
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159 | +# bit31-28: TRTP |
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160 | + |
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161 | +DATA 0xFFD0140C 0x00000a33 # DDR Timing (High) |
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162 | +# bit6-0: TRFC |
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163 | +# bit8-7: TR2R |
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164 | +# bit10-9: TR2W |
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165 | +# bit12-11: TW2W |
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166 | +# bit31-13: zero required |
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167 | + |
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168 | +DATA 0xFFD01410 0x0000000c # DDR Address Control |
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169 | +# bit1-0: 01, Cs0width=x8 |
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170 | +# bit3-2: 10, Cs0size=1Gb |
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171 | +# bit5-4: 01, Cs1width=x8 |
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172 | +# bit7-6: 10, Cs1size=1Gb |
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173 | +# bit9-8: 00, Cs2width=nonexistent |
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174 | +# bit11-10: 00, Cs2size =nonexistent |
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175 | +# bit13-12: 00, Cs3width=nonexistent |
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176 | +# bit15-14: 00, Cs3size =nonexistent |
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177 | +# bit16: 0, Cs0AddrSel |
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178 | +# bit17: 0, Cs1AddrSel |
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179 | +# bit18: 0, Cs2AddrSel |
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180 | +# bit19: 0, Cs3AddrSel |
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181 | +# bit31-20: 0 required |
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182 | + |
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183 | +DATA 0xFFD01414 0x00000000 # DDR Open Pages Control |
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184 | +# bit0: 0, OpenPage enabled |
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185 | +# bit31-1: 0 required |
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186 | + |
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187 | +DATA 0xFFD01418 0x00000000 # DDR Operation |
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188 | +# bit3-0: 0x0, DDR cmd |
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189 | +# bit31-4: 0 required |
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190 | + |
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191 | +DATA 0xFFD0141C 0x00000652 # DDR Mode |
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192 | +# bit2-0: 2, BurstLen=2 required |
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193 | +# bit3: 0, BurstType=0 required |
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194 | +# bit6-4: 4, CL=5 |
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195 | +# bit7: 0, TestMode=0 normal |
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196 | +# bit8: 0, DLL reset=0 normal |
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197 | +# bit11-9: 6, auto-precharge write recovery ???????????? |
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198 | +# bit12: 0, PD must be zero |
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199 | +# bit31-13: 0 required |
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200 | + |
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201 | +DATA 0xFFD01420 0x00000004 # DDR Extended Mode |
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202 | +# bit0: 0, DDR DLL enabled |
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203 | +# bit1: 0, DDR drive strenght normal |
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204 | +# bit2: 0, DDR ODT control lsd (disabled) |
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205 | +# bit5-3: 000, required |
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206 | +# bit6: 1, DDR ODT control msb, (disabled) |
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207 | +# bit9-7: 000, required |
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208 | +# bit10: 0, differential DQS enabled |
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209 | +# bit11: 0, required |
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210 | +# bit12: 0, DDR output buffer enabled |
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211 | +# bit31-13: 0 required |
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212 | + |
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213 | +DATA 0xFFD01424 0x0000F17F # DDR Controller Control High |
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214 | +# bit2-0: 111, required |
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215 | +# bit3 : 1 , MBUS Burst Chop disabled |
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216 | +# bit6-4: 111, required |
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217 | +# bit7 : 0 |
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218 | +# bit8 : 1 , add writepath sample stage, must be 1 for DDR freq >= 300MHz |
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219 | +# bit9 : 0 , no half clock cycle addition to dataout |
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220 | +# bit10 : 0 , 1/4 clock cycle skew enabled for addr/ctl signals |
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221 | +# bit11 : 0 , 1/4 clock cycle skew disabled for write mesh |
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222 | +# bit15-12: 1111 required |
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223 | +# bit31-16: 0 required |
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224 | + |
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225 | +DATA 0xFFD01428 0x00085520 # DDR2 ODT Read Timing (default values) |
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226 | +DATA 0xFFD0147C 0x00008552 # DDR2 ODT Write Timing (default values) |
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227 | + |
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228 | + |
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229 | +DATA 0xFFD01504 0x0FFFFFF1 # CS[0]n Size |
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230 | +#DATA 0xFFD01500 0x00000000 # CS[0]n Base address to 0x0 |
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231 | +# bit0: 1, Window enabled |
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232 | +# bit1: 0, Write Protect disabled |
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233 | +# bit3-2: 00, CS0 hit selected |
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234 | +# bit23-4: ones, required |
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235 | +# bit31-24: 0x0F, Size (i.e. 256MB) |
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236 | + |
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237 | +DATA 0xFFD01508 0x10000000 # CS[1]n Base address to 256Mb |
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238 | +DATA 0xFFD0150C 0x00000000 # CS[2]n Size, window disabled KAZ z 400db |
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239 | +DATA 0xFFD01514 0x00000000 # CS[3]n Size, window disabled |
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240 | + |
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241 | +DATA 0xFFD0151C 0x00000000 # DDR ODT Control (Low) |
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242 | +DATA 0xFFD01494 0x00120012 # DDR ODT Control (High) KAZ z nowy STATIC_SDRAM_ODT_CTRL_LOW |
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243 | +# bit1-0: 00, ODT0 controlled by ODT Control (low) register above |
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244 | +# bit3-2: 01, ODT1 active NEVER! |
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245 | +# bit31-4: zero, required |
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246 | + |
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247 | +DATA 0xFFD01498 0x00000000 # CPU ODT Control KAZ STATIC_SDRAM_ODT_CTRL_HI |
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248 | +DATA 0xFFD0149C 0x0000E403 # DDR Initialization Control KAZ STATIC_SDRAM_DUNIT_ODT_CTRL |
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249 | +DATA 0xFFD01480 0x00000001 # DDR Initialization Control |
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250 | +#bit0=1, enable DDR init upon this register write |
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251 | + |
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252 | +# End of Header extension |
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253 | +DATA 0x0 0x0 |
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254 | --- /dev/null |
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255 | +++ b/board/zyxel/nsa310/nsa310.c |
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256 | @@ -0,0 +1,190 @@ |
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257 | +/* |
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258 | + * Copyright (C) 2013 Rafal Kazmierowski |
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259 | + * |
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260 | + * Based on NSA320.c Peter Schildmann <linux@schildmann.info> |
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261 | + * originally written by |
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262 | + * Marvell Semiconductor <www.marvell.com> |
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263 | + * Written-by: Prafulla Wadaskar <prafulla@marvell.com> |
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264 | + * |
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265 | + * See file CREDITS for list of people who contributed to this |
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266 | + * project. |
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267 | + * |
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268 | + * This program is free software; you can redistribute it and/or |
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269 | + * modify it under the terms of the GNU General Public License as |
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270 | + * published by the Free Software Foundation; either version 2 of |
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271 | + * the License, or (at your option) any later version. |
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272 | + * |
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273 | + * This program is distributed in the hope that it will be useful, |
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274 | + * but WITHOUT ANY WARRANTY; without even the implied warranty of |
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275 | + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
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276 | + * GNU General Public License for more details. |
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277 | + * |
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278 | + * You should have received a copy of the GNU General Public License |
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279 | + * along with this program; if not, write to the Free Software |
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280 | + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, |
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281 | + * MA 02110-1301 USA |
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282 | + */ |
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283 | + |
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284 | +#include <common.h> |
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285 | +#include <miiphy.h> |
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286 | +#include <asm/arch/cpu.h> |
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287 | +#include <asm/arch/soc.h> |
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288 | +#include <asm/arch/mpp.h> |
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289 | +#include <asm/io.h> |
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290 | +#include "nsa310.h" |
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291 | + |
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292 | +DECLARE_GLOBAL_DATA_PTR; |
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293 | + |
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294 | +int board_early_init_f(void) |
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295 | +{ |
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296 | + /* |
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297 | + * default gpio configuration |
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298 | + * There are maximum 64 gpios controlled through 2 sets of registers |
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299 | + * the below configuration configures mainly initial LED status |
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300 | + */ |
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301 | + mvebu_config_gpio(NSA310_VAL_LOW, NSA310_VAL_HIGH, |
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302 | + NSA310_OE_LOW, NSA310_OE_HIGH); |
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303 | + |
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304 | + /* Multi-Purpose Pins Functionality configuration */ |
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305 | + /* (all LEDs & power off active high) */ |
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306 | + static const u32 kwmpp_config[] = { |
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307 | + MPP0_NF_IO2, |
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308 | + MPP1_NF_IO3, |
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309 | + MPP2_NF_IO4, |
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310 | + MPP3_NF_IO5, |
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311 | + MPP4_NF_IO6, |
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312 | + MPP5_NF_IO7, |
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313 | + MPP6_SYSRST_OUTn, |
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314 | + MPP7_GPO, |
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315 | + MPP8_TW_SDA, /* PCF8563 RTC chip */ |
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316 | + MPP9_TW_SCK, /* connected to TWSI */ |
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317 | + MPP10_UART0_TXD, |
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318 | + MPP11_UART0_RXD, |
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319 | + MPP12_GPO, /* SATA2 LED (green) */ |
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320 | + MPP13_GPIO, /* SATA2 LED (red) */ |
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321 | + MPP14_GPIO, /* MCU DATA pin (in) */ |
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322 | + MPP15_GPIO, /* USB LED (green) */ |
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323 | + MPP16_GPIO, /* MCU CLK pin (out) */ |
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324 | + MPP17_GPIO, /* MCU ACT pin (out) */ |
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325 | + MPP18_NF_IO0, |
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326 | + MPP19_NF_IO1, |
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327 | + MPP20_GPIO, |
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328 | + MPP21_GPIO, /* USB LED (red)-Power*/ |
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329 | + MPP22_GPIO, |
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330 | + MPP23_GPIO, |
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331 | + MPP24_GPIO, |
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332 | + MPP25_GPIO, |
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333 | + MPP26_GPIO, |
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334 | + MPP27_GPIO, |
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335 | + MPP28_GPIO, /* SYS LED (green) */ |
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336 | + MPP29_GPIO, /* SYS LED (red) */ |
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337 | + MPP30_GPIO, |
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338 | + MPP31_GPIO, |
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339 | + MPP32_GPIO, |
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340 | + MPP33_GPIO, |
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341 | + MPP34_GPIO, |
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342 | + MPP35_GPIO, |
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343 | + MPP36_GPIO, /* Reset button */ |
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344 | + MPP37_GPIO, /* Copy button */ |
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345 | + MPP38_GPIO, /* VID B0 */ |
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346 | + MPP39_GPIO, /* COPY LED (green) */ |
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347 | + MPP40_GPIO, /* COPY LED (red) */ |
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348 | + MPP41_GPIO, /* SATA1 LED (green) */ |
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349 | + MPP42_GPIO, /* SATA1 LED (red) */ |
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350 | + MPP43_GPIO, /* HTP pin */ |
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351 | + MPP44_GPIO, /* Buzzer */ |
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352 | + MPP45_GPIO, /* VID B1 */ |
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353 | + MPP46_GPIO, /* Power button */ |
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354 | + MPP47_GPIO, /* Power resume data */ |
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355 | + MPP48_GPIO, /* Power off */ |
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356 | + MPP49_GPIO, /* Power resume clock */ |
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357 | + 0 |
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358 | + }; |
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359 | + kirkwood_mpp_conf(kwmpp_config,NULL); |
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360 | + return 0; |
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361 | +} |
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362 | + |
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363 | +int board_init(void) |
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364 | +{ |
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365 | + /* address of boot parameters */ |
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366 | + gd->bd->bi_boot_params = mvebu_sdram_bar(0) + 0x100; |
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367 | + |
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368 | + return 0; |
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369 | +} |
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370 | + |
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371 | +#ifdef CONFIG_RESET_PHY_R |
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372 | +/* Configure and enable MV88E1318 PHY */ |
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373 | +void reset_phy(void) |
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374 | +{ |
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375 | + u16 reg; |
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376 | + u16 devadr; |
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377 | + char *name = "egiga0"; |
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378 | + |
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379 | + if (miiphy_set_current_dev(name)) |
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380 | + return; |
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381 | + |
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382 | + /* command to read PHY dev address */ |
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383 | + if (miiphy_read(name, 0xEE, 0xEE, (u16 *) &devadr)) { |
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384 | + printf("Err..%s could not read PHY dev address\n", |
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385 | + __FUNCTION__); |
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386 | + return; |
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387 | + } |
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388 | + |
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389 | + /* Set RGMII delay */ |
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390 | + miiphy_write(name, devadr, MV88E1318_PGADR_REG, 2); |
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391 | + miiphy_read(name, devadr, MV88E1318_MAC_CTRL_REG, ®); |
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392 | + reg |= (MV88E1318_RGMII_RXTM_CTRL | MV88E1318_RGMII_TXTM_CTRL); |
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393 | + miiphy_write(name, devadr, MV88E1318_MAC_CTRL_REG, reg); |
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394 | + miiphy_write(name, devadr, MV88E1318_PGADR_REG, 0); |
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395 | + |
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396 | + /* reset the phy */ |
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397 | + miiphy_reset(name, devadr); |
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398 | + |
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399 | + printf("MV88E1318 PHY initialized on %s\n", name); |
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400 | +} |
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401 | +#endif /* CONFIG_RESET_PHY_R */ |
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402 | + |
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403 | +#ifdef CONFIG_SHOW_BOOT_PROGRESS |
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404 | +void show_boot_progress(int val) |
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405 | +{ |
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406 | + struct kwgpio_registers *gpio0 = (struct kwgpio_registers *)MVEBU_GPIO0_BASE; |
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407 | + u32 dout0 = readl(&gpio0->dout); |
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408 | + u32 blen0 = readl(&gpio0->blink_en); |
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409 | + |
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410 | + struct kwgpio_registers *gpio1 = (struct kwgpio_registers *)MVEBU_GPIO1_BASE; |
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411 | + u32 dout1 = readl(&gpio1->dout); |
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412 | + u32 blen1 = readl(&gpio1->blink_en); |
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413 | + |
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414 | + switch (val) { |
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415 | + case BOOTSTAGE_ID_DECOMP_IMAGE: |
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416 | + writel(blen0 & ~(SYS_GREEN_LED | SYS_RED_LED), &gpio0->blink_en); |
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417 | + writel((dout0 & ~SYS_GREEN_LED) | SYS_RED_LED, &gpio0->dout); |
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418 | + break; |
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419 | + case BOOTSTAGE_ID_RUN_OS: |
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420 | + writel(dout0 & ~SYS_RED_LED, &gpio0->dout); |
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421 | + writel(blen0 | SYS_GREEN_LED, &gpio0->blink_en); |
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422 | + break; |
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423 | + case BOOTSTAGE_ID_NET_START: |
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424 | + writel(dout1 & ~COPY_RED_LED, &gpio1->dout); |
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425 | + writel((blen1 & ~COPY_RED_LED) | COPY_GREEN_LED, &gpio1->blink_en); |
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426 | + break; |
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427 | + case BOOTSTAGE_ID_NET_LOADED: |
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428 | + writel(blen1 & ~(COPY_RED_LED | COPY_GREEN_LED), &gpio1->blink_en); |
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429 | + writel((dout1 & ~COPY_RED_LED) | COPY_GREEN_LED, &gpio1->dout); |
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430 | + break; |
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431 | + case -BOOTSTAGE_ID_NET_NETLOOP_OK: |
||
432 | + case -BOOTSTAGE_ID_NET_LOADED: |
||
433 | + writel(dout1 & ~COPY_GREEN_LED, &gpio1->dout); |
||
434 | + writel((blen1 & ~COPY_GREEN_LED) | COPY_RED_LED, &gpio1->blink_en); |
||
435 | + break; |
||
436 | + default: |
||
437 | + if (val < 0) { |
||
438 | + /* error */ |
||
439 | + printf("Error occured, error code = %d\n", -val); |
||
440 | + writel(dout0 & ~SYS_GREEN_LED, &gpio0->dout); |
||
441 | + writel(blen0 | SYS_RED_LED, &gpio0->blink_en); |
||
442 | + } |
||
443 | + break; |
||
444 | + } |
||
445 | +} |
||
446 | +#endif |
||
447 | --- /dev/null |
||
448 | +++ b/board/zyxel/nsa310/nsa310.h |
||
449 | @@ -0,0 +1,56 @@ |
||
450 | +/* |
||
451 | + * Copyright (C) 2013 Rafal Kazmierowski |
||
452 | + * |
||
453 | + * Based on Peter Schildmann <linux@schildmann.info> |
||
454 | + * and guruplug.h originally written by |
||
455 | + * Siddarth Gore <gores@marvell.com> |
||
456 | + * (C) Copyright 2009 |
||
457 | + * Marvell Semiconductor <www.marvell.com> |
||
458 | + * |
||
459 | + * See file CREDITS for list of people who contributed to this |
||
460 | + * project. |
||
461 | + * |
||
462 | + * This program is free software; you can redistribute it and/or |
||
463 | + * modify it under the terms of the GNU General Public License as |
||
464 | + * published by the Free Software Foundation; either version 2 of |
||
465 | + * the License, or (at your option) any later version. |
||
466 | + * |
||
467 | + * This program is distributed in the hope that it will be useful, |
||
468 | + * but WITHOUT ANY WARRANTY; without even the implied warranty of |
||
469 | + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
||
470 | + * GNU General Public License for more details. |
||
471 | + * |
||
472 | + * You should have received a copy of the GNU General Public License |
||
473 | + * along with this program; if not, write to the Free Software |
||
474 | + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, |
||
475 | + * MA 02110-1301 USA |
||
476 | + */ |
||
477 | + |
||
478 | +#ifndef __NSA310_H |
||
479 | +#define __NSA310_H |
||
480 | + |
||
481 | +/* GPIO's */ |
||
482 | +#define SYS_GREEN_LED (1 << 28) |
||
483 | +#define SYS_RED_LED (1 << 29) |
||
484 | +#define SATA1_GREEN_LED (1ULL << 41) |
||
485 | +#define SATA1_RED_LED (1ULL << 42) |
||
486 | +#define SATA2_GREEN_LED (1 << 12) |
||
487 | +#define SATA2_RED_LED (1 << 13) |
||
488 | +#define USB_GREEN_LED (1 << 15) |
||
489 | +#define USB_RED_LED (1 << 21) |
||
490 | +#define COPY_GREEN_LED (1ULL << 39) |
||
491 | +#define COPY_RED_LED (1ULL << 40) |
||
492 | + |
||
493 | +#define NSA310_OE_LOW (0) |
||
494 | +#define NSA310_VAL_LOW (SYS_GREEN_LED) |
||
495 | +#define NSA310_OE_HIGH (((COPY_GREEN_LED | COPY_RED_LED | \ |
||
496 | + SATA1_GREEN_LED | SATA1_RED_LED)) >> 32UL) |
||
497 | +#define NSA310_VAL_HIGH (0) |
||
498 | + |
||
499 | +/* PHY related */ |
||
500 | +#define MV88E1318_MAC_CTRL_REG 21 |
||
501 | +#define MV88E1318_PGADR_REG 22 |
||
502 | +#define MV88E1318_RGMII_TXTM_CTRL (1 << 4) |
||
503 | +#define MV88E1318_RGMII_RXTM_CTRL (1 << 5) |
||
504 | + |
||
505 | +#endif /* __NSA310_H */ |
||
506 | --- /dev/null |
||
507 | +++ b/configs/nsa310_defconfig |
||
3 | office | 508 | @@ -0,0 +1,37 @@ |
1 | office | 509 | +CONFIG_ARM=y |
510 | +CONFIG_KIRKWOOD=y |
||
511 | +CONFIG_SYS_TEXT_BASE=0x600000 |
||
512 | +CONFIG_TARGET_NSA310=y |
||
513 | +CONFIG_IDENT_STRING="\nZyXEL NSA310 1-Bay Power Media Server" |
||
514 | +CONFIG_BOOTDELAY=3 |
||
515 | +CONFIG_SYS_PROMPT="NSA310> " |
||
516 | +# CONFIG_CMD_IMLS is not set |
||
517 | +# CONFIG_CMD_FLASH is not set |
||
518 | +CONFIG_SYS_NS16550=y |
||
519 | +CONFIG_CMD_FDT=y |
||
520 | +CONFIG_OF_LIBFDT=y |
||
521 | +CONFIG_CMD_SETEXPR=y |
||
522 | +CONFIG_CMD_DHCP=y |
||
523 | +CONFIG_CMD_MII=y |
||
524 | +CONFIG_CMD_PING=y |
||
525 | +CONFIG_CMD_DNS=y |
||
526 | +CONFIG_CMD_SNTP=y |
||
527 | +CONFIG_CMD_USB=y |
||
528 | +CONFIG_CMD_DATE=y |
||
529 | +CONFIG_CMD_EXT2=y |
||
530 | +CONFIG_CMD_EXT4=y |
||
531 | +CONFIG_CMD_FAT=y |
||
532 | +CONFIG_CMD_JFFS2=y |
||
533 | +CONFIG_MTDPARTS_DEFAULT="mtdparts=orion_nand:0x0c0000(uboot),0x80000(uboot_env),0x7ec0000(ubi)" |
||
534 | +CONFIG_CMD_MTDPARTS=y |
||
535 | +CONFIG_CMD_ENV=y |
||
536 | +CONFIG_CMD_NAND=y |
||
537 | +CONFIG_EFI_PARTITION=y |
||
538 | +CONFIG_ENV_IS_IN_NAND=y |
||
539 | +CONFIG_CMD_UBI=y |
||
540 | +CONFIG_USB=y |
||
541 | +CONFIG_USB_EHCI_HCD=y |
||
542 | +CONFIG_USB_STORAGE=y |
||
543 | +CONFIG_LZMA=y |
||
544 | +CONFIG_LZO=y |
||
545 | +CONFIG_SYS_LONGHELP=y |
||
546 | --- /dev/null |
||
547 | +++ b/include/configs/nsa310.h |
||
3 | office | 548 | @@ -0,0 +1,119 @@ |
1 | office | 549 | +/* Copyright (C) 2015-2016 bodhi <mibodhi@gmail.com> |
550 | + * |
||
551 | + * Based on |
||
552 | + * Copyright (C) 2012 Peter Schildmann <linux@schildmann.info> |
||
553 | + * |
||
554 | + * Based on guruplug.h originally written by |
||
555 | + * Siddarth Gore <gores@marvell.com> |
||
556 | + * (C) Copyright 2009 |
||
557 | + * Marvell Semiconductor <www.marvell.com> |
||
558 | + * |
||
559 | + * See file CREDITS for list of people who contributed to this |
||
560 | + * project. |
||
561 | + * |
||
562 | + * This program is free software; you can redistribute it and/or |
||
563 | + * modify it under the terms of the GNU General Public License as |
||
564 | + * published by the Free Software Foundation; either version 2 of |
||
565 | + * the License, or (at your option) any later version. |
||
566 | + * |
||
567 | + * This program is distributed in the hope that it will be useful, |
||
568 | + * but WITHOUT ANY WARRANTY; without even the implied warranty of |
||
569 | + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
||
570 | + * GNU General Public License for more details. |
||
571 | + * |
||
572 | + * You should have received a copy of the GNU General Public License |
||
573 | + * along with this program; if not, write to the Free Software |
||
574 | + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, |
||
575 | + * MA 02110-1301 USA |
||
576 | + */ |
||
577 | + |
||
578 | +#ifndef _CONFIG_NSA310_H |
||
579 | +#define _CONFIG_NSA310_H |
||
580 | + |
||
581 | +/* |
||
582 | + * High Level Configuration Options (easy to change) |
||
583 | + */ |
||
584 | +#define CONFIG_FEROCEON_88FR131 /* CPU Core subversion */ |
||
585 | +#define CONFIG_KW88F6281 /* SOC Name */ |
||
586 | + |
||
587 | +#define CONFIG_SKIP_LOWLEVEL_INIT /* disable board lowlevel_init */ |
||
588 | + |
||
589 | +/* |
||
590 | + * Misc Configuration Options |
||
591 | + */ |
||
592 | +#define CONFIG_SHOW_BOOT_PROGRESS 1 /* boot progess display (LED's) */ |
||
593 | + |
||
594 | +/* |
||
595 | + * Commands configuration |
||
596 | + */ |
||
597 | +#define CONFIG_PREBOOT |
||
598 | + |
||
599 | +/* |
||
600 | + * mv-common.h should be defined after CMD configs since it used them |
||
601 | + * to enable certain macros |
||
602 | + */ |
||
603 | +#include "mv-common.h" |
||
604 | + |
||
605 | +/* |
||
606 | + * Environment variables configurations |
||
607 | + */ |
||
608 | +#ifdef CONFIG_CMD_NAND |
||
609 | +#define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K */ |
||
610 | +#endif |
||
611 | + |
||
612 | +/* max 4k env size is enough, but in case of nand |
||
613 | + * it has to be rounded to sector size |
||
614 | + */ |
||
615 | +#define CONFIG_ENV_SIZE 0x20000 /* 128k */ |
||
616 | +#define CONFIG_ENV_ADDR 0xc0000 |
||
617 | +#define CONFIG_ENV_OFFSET 0xc0000 /* env starts here */ |
||
618 | + |
||
619 | +/* |
||
620 | + * Default environment variables |
||
621 | + */ |
||
622 | +#define CONFIG_BOOTCOMMAND \ |
||
623 | + "ubi part ubi; " \ |
||
624 | + "ubi read 0x800000 kernel; " \ |
||
625 | + "bootm 0x800000" |
||
626 | + |
||
627 | +#define CONFIG_EXTRA_ENV_SETTINGS \ |
||
628 | + "console=console=ttyS0,115200\0" \ |
||
629 | + "mtdids=nand0=orion_nand\0" \ |
||
630 | + "mtdparts="CONFIG_MTDPARTS_DEFAULT "\0" \ |
||
631 | + "bootargs_root=\0" |
||
632 | + |
||
633 | +/* |
||
634 | + * Ethernet Driver configuration |
||
635 | + */ |
||
636 | +#ifdef CONFIG_CMD_NET |
||
637 | +#define CONFIG_NETCONSOLE |
||
638 | +#define CONFIG_NET_MULTI |
||
639 | +#define CONFIG_MVGBE_PORTS {1, 0} /* enable port 0 only */ |
||
640 | +#define CONFIG_PHY_BASE_ADR 0x1 |
||
641 | +#define CONFIG_RESET_PHY_R |
||
642 | +#endif /* CONFIG_CMD_NET */ |
||
643 | + |
||
644 | +/* |
||
645 | + * SATA Driver configuration |
||
646 | + */ |
||
647 | +#ifdef CONFIG_MVSATA_IDE |
||
648 | +#define CONFIG_SYS_ATA_IDE0_OFFSET MV_SATA_PORT0_OFFSET |
||
649 | +#define CONFIG_SYS_ATA_IDE1_OFFSET MV_SATA_PORT1_OFFSET |
||
650 | +#endif /* CONFIG_MVSATA_IDE */ |
||
651 | + |
||
652 | +/* |
||
653 | + * File system |
||
654 | + */ |
||
655 | +#define CONFIG_JFFS2_NAND |
||
656 | +#define CONFIG_JFFS2_LZO |
||
3 | office | 657 | +#define CONFIG_MTD_DEVICE /* needed for mtdparts commands */ |
658 | +#define CONFIG_MTD_PARTITIONS |
||
1 | office | 659 | + |
660 | +/* |
||
661 | + * Date Time |
||
662 | + */ |
||
663 | +#ifdef CONFIG_CMD_DATE |
||
664 | +#define CONFIG_RTC_MV |
||
665 | +#endif /* CONFIG_CMD_DATE */ |
||
666 | + |
||
667 | +#endif /* _CONFIG_NSA310_H */ |